1. Field of the Invention
This invention is related to integrated circuits formed on a semiconductor substrate. More particularly, this invention is related to integrated circuits having multiple selectable functions. These functions are selectable during operation by xe2x80x9csoftwarexe2x80x9d programming.
1. Description of the Related Art
The structures of a field programmable gate array (FPGA) and programmed logic devices (PLD) are well known in the art. An FPGA and PLD each have configurable logic blocks (CLB) that will perform a Boolean logic operation on a group of input signals to perform a single complex logical function. The configurable logic blocks are then interconnected to form even more complex logic structures. The interconnection between the configurable logic blocks may be created by physically destroying fuses to break undesired connections or by activating pass transistors between wiring segments routed on the semiconductor substrate.
U.S. Pat. No. 5,740,069 (Agrawal et al.) describes a programmable integrated circuit that includes configurable logic blocks (CLB""s), configurable input/output blocks (IOB""s) and an interconnect network for providing program-defined routing of signals between the CLB""s and IOB""s. The interconnect network includes direct connect means for providing programmably-selectable, dedicated connections between a first CLB and one or more adjacent CLB""s and further between a first CLB and one or more CLB""s. The interconnect network also includes peripheral direct connect means for providing programmably selectable, dedicated connections between a first configurable IOB and first and second CLB""s.
U.S. patent application Ser. No. 09/246,303, filed Feb. 8, 1999, teaches an integrated circuit module that has a common function known good integrated circuit die with selectable functions. The selectable functions are selected during assembly of the known good integrated circuit die. The known good integrated circuit die is mounted to a second level substrate. The second level substrate has wiring connections to the input/output pads of the known good integrated circuit die that select desired input functions and output functions.
Further, the wiring connections on the second level substrate provide signal paths to transfer signals to the desired input function and signals from the desired output function, and signals to and from the common functions. In addition, the wiring connections form connections between the input/output pads and external circuitry. To select the desired input functions and the desired output functions, appropriate logic states are applied to input/output pads connected to a function selector to configure a functional operation of the integrated circuit module. The second level module substrate has connector pins to provide physical and electrical connections between the external circuitry and the wiring connections on the second level substrate.
U.S. Pat. No. 5,360,992 (Lowery et al.) illustrates a semiconductor package which allows pinouts and bond options to be customized after encasement of a semiconductor die. The semiconductor package has two assemblies in a first embodiment and an optional third assembly in a second embodiment.
As semiconductor processing technology has improved, the number of electronic components has increased until it is now possible to incorporate multiple complete functions on an integrated circuit die. The concept of being able to have multiple selectable functions incorporated on a single integrated circuit die is known in the art. U.S. Pat. No. 5,511,182 (Le et al.) teaches a pin configuration logic circuit. The pin configuration logic circuit has a pin function register which defines a selected pin function, such as chip enable, write enable, and output enable to be provided as a chip select signal. The logic circuit allows an arbitrary pipeline length by causing the chip select signal to obey only the timing of the active cycle. For a two-deep access pipeline the logic circuit marks whether a first or a second cycle owns the pin. The pin configuration logic circuit uses the timing associated with the selected pin function to provide the chip select signal during the first cycle if the attributes of the cycle, such as an access to a region programmed in the pin function register, are met. During the second cycle, the pin configuration logic circuit further obeys the timing associated with the selected pin function if the attributes of that cycle are also met.
Further, the concept of reconfigurable circuit functions has been explored in the art. xe2x80x9cTowards the Realistic Virtual Hardwarexe2x80x9d, Shibata et al., Innovative Architecture for Future Generation High-Performance Processors and Systems, October 1997, pp. 50-55 describes a virtual hardware system that executes dataflow algorithms. It is based on an MPLD (Multifunction Programming Logic Device), an extended FPGA (Field Programmable Gate Array) that implements multiple sets of functions as configurations of a single chip. An algorithm to be executed on the virtual hardware is written in the DFC dataflow language and then translated into a collection of FPGA configurations, each representing a page-sized sub graph of the dataflow graph. Although an emulation system and software environment for the virtual hardware has been developed it has tended to be an unrealistic system due to the difficulty of the MPLD implementation. However, with recent technologies of semiconductors, FPGA and DRAM can be implemented into a single LSI chip. By using the common buffer of the DRAM array as a configuration memory of an FPGA, replacement of configuration data can be done at almost the same speed as an MPU. Compared with the MPLD approach, a large amount of data can be stored in the integrated DRAM.
While Shibata, et al. describes a configurable digital logic system, mixed signal (analog and digital) applications can be designed for reconfiguration. xe2x80x9cReconfigurable Signal Processing ASIC Architecture For High Speed Data Communicationsxe2x80x9d, Grayver, et al., Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, June 1998, ISCAS ""98, Vol. 4, pp. 389-392 illustrates a flexible and reconfigurable signal processing ASIC architecture. The proposed architecture can be used to realize any one of several functional blocks needed for the physical layer implementation of high speed data communication systems operating at symbol rates over 60M samples/sec. In fact, multiple instances of a chip based on this architecture, each operating in a different mode, can be used to realize the entire physical layer of high-speed data communication systems. The architecture features the following modes (functions); real and complex FIR/IIR filtering, least mean square (LMS) based adaptive filtering, Discrete Fourier Transforms (DFT) and direct digital frequency synthesis (DDFS), at up to 60M samples/sec. All of the modes are mapped onto a common, regular datapath with minimal configuration logic and routing. Multiple chips operating in the same mode can be cascaded to allow for larger blocks.
An object of this invention is to provide an integrated circuit having multiple selectable functions that can be chosen by electrical signals controlled by software programming.
Another object of this invention is to provide a circuit to allow ease of programming of selected functions of the multiple selectable function on an integrated circuit chip.
To accomplish these and other functions, an electrically programmable multiple selectable function integrated circuit module has a plurality of input connectors to receive a plurality of input data signals. The plurality of input data signals transferred through the plurality of input connectors to a plurality of optionally selectable function circuits. The outputs of the plurality of optionally selectable function circuits are either interconnected to each other or connected to a plurality of output connectors to transmit manipulated output data signals to external circuitry.
The electrically programmable multiple selectable function integrated circuit module has at least one configuration connector connected to a function configuration circuit to receive electrical configuration signals indicating which of the optionally selectable function circuits are to be elected to manipulate the input data signals. The function configuration circuit is connected to the optionally selectable function circuits to selectively elect which of the optionally selectable function circuits are to manipulate the input data signals;
The electrically programmable multiple selectable function integrated circuit module optionally has a plurality of common function connectors to receive common input data signals and transmit common output data signals. The common function circuit is connected to the common function connectors and the plurality of optionally selectable function circuits to manipulate the common data signals, and transmit the common output data signals to the selectable function circuits.
The electrically programmable multiple selectable function integrated circuit module has the plurality of optionally selectable function circuits, the function configuration circuit, and the common function circuit fabricated on at least one semiconductor substrate. The semiconductor substrate has input/output connectors formed from a ball-grid array. The input/output connectors are the input connectors, the output connectors, the function configuration connectors, and the common function connectors.
The electrical configuration signal sets the electrically programmable multiple selectable function integrated circuit module to a program state, whereby the input data signals convey a programmed configuration to select the desired optionally selectable function circuits. The configuration circuit includes a function selector placed between the input connectors and the optionally selectable function circuits and between the optionally selectable function circuits and the output connectors to select which of the optionally selectable function circuits are to manipulate the input data signals and which of the optionally selectable function circuits are to transmit the manipulated output data signals. The configuration circuit also includes a function programming circuit to receive, interpret, and retain the input data signals containing the data to identify those optionally selectable function circuits to be selected. The configuration circuit further has a mode selector to transfer the integrated circuit module from an operational state to a program state that disconnects the input connectors from the optionally selectable function circuits and connects the input connectors to the function programming circuit such that the input data signal is interpreted to identify those optionally selectable function circuits that are to manipulate the input data signal during the operational state.
The function programming circuit has a plurality of latch circuits. Each latch circuit has an input to receive the input data signal, a memory element to retain the data to identify the optionally selectable function circuits, and an output to transmit the identity of those optionally selectable function circuits that are elected to manipulate the input data.
The mode selector is comprised of a plurality of switching circuits. Each switching circuit has an input terminal connected to one of the input connectors, a first output terminal connected to the optionally selectable function circuits through the mode selection circuit, a second output terminal connected to the function programming circuit, and a control terminal connected to the configuration connector to receive the electrical configuration signal. The second output terminal transfers the identity of those optionally selectable function circuits to the function programming circuit. The control terminal changes the integrated circuit module between the operational state to the program state.